8.5 KiB
| title | chunk | source | category | tags | date_saved | instance |
|---|---|---|---|---|---|---|
| Canonical normal form | 2/4 | https://en.wikipedia.org/wiki/Canonical_normal_form | reference | science, encyclopedia | 2026-05-05T14:45:04.681873+00:00 | kb-cron |
Observing that the rows that have an output of 0 are the 1st, 2nd, 3rd, and 5th, we can write co as a product of maxterms
M
0
,
M
1
,
M
2
{\displaystyle M_{0},M_{1},M_{2}}
and
M
4
{\displaystyle M_{4}}
. If we wish to verify this:
c
o
(
c
i
,
x
,
y
)
=
M
0
M
1
M
2
M
4
=
(
c
i
+
x
+
y
)
(
c
i
+
x
+
y
′
)
(
c
i
+
x
′
+
y
)
(
c
i
′
+
x
+
y
)
{\displaystyle co(ci,x,y)=M_{0}M_{1}M_{2}M_{4}=(ci+x+y)(ci+x+y')(ci+x'+y)(ci'+x+y)}
evaluated for all 8 combinations of the three variables will match the table.
== Minimal PoS and SoP forms == It is often the case that the canonical minterm form is equivalent to a smaller SoP form. This smaller form would still consist of a sum of product terms, but have fewer product terms and/or product terms that contain fewer variables. For example, the following 3-variable function:
has the canonical minterm representation
f
=
a
′
b
c
+
a
b
c
{\displaystyle f=a'bc+abc}
, but it has an equivalent SoP form
f
=
b
c
{\displaystyle f=bc}
. In this trivial example, it is obvious that
b
c
=
a
′
b
c
+
a
b
c
{\displaystyle bc=a'bc+abc}
, and the smaller form has both fewer product terms and fewer variables within each term. The minimal SoP representations of a function according to this notion of "smallest" are referred to as minimal SoP forms. In general, there may be multiple minimal SoP forms, none clearly smaller or larger than another. In a similar manner, a canonical maxterm form can be reduced to various minimal PoS forms. While this example was simplified by applying normal algebraic methods [
f
=
(
a
′
+
a
)
b
c
{\displaystyle f=(a'+a)bc}
], in less obvious cases a convenient method for finding minimal PoS/SoP forms of a function with up to four variables is using a Karnaugh map. The Quine–McCluskey algorithm can solve slightly larger problems. The field of logic optimization developed from the problem of finding optimal implementations of Boolean functions, such as minimal PoS and SoP forms.
== Application example == The sample truth tables for minterms and maxterms above are sufficient to establish the canonical form for a single bit position in the addition of binary numbers, but are not sufficient to design the digital logic unless your inventory of gates includes AND and OR. Where performance is an issue (as in the Apollo Guidance Computer), the available parts are more likely to be NAND and NOR because of the complementing action inherent in transistor logic. The values are defined as voltage states, one near ground and one near the DC supply voltage Vcc, e.g. +5 VDC. If the higher voltage is defined as the 1 "true" value, a NOR gate is the simplest possible useful logical element. Specifically, a 3-input NOR gate may consist of 3 bipolar junction transistors with their emitters all grounded, their collectors tied together and linked to Vcc through a load impedance. Each base is connected to an input signal, and the common collector point presents the output signal. Any input that is a 1 (high voltage) to its base shorts its transistor's emitter to its collector, causing current to flow through the load impedance, which brings the collector voltage (the output) very near to ground. That result is independent of the other inputs. Only when all 3 input signals are 0 (low voltage) do the emitter-collector impedances of all 3 transistors remain very high. Then very little current flows, and the voltage-divider effect with the load impedance imposes on the collector point a high voltage very near to Vcc. The complementing property of these gate circuits may seem like a drawback when trying to implement a function in canonical form, but there is a compensating bonus: such a gate with only one input implements the complementing function, which is required frequently in digital logic. This example assumes the Apollo parts inventory: 3-input NOR gates only, but the discussion is simplified by supposing that 4-input NOR gates are also available (in Apollo, those were compounded out of pairs of 3-input NORs).
=== Canonical and non-canonical consequences of NOR gates === A set of 8 NOR gates, if their inputs are all combinations of the direct and complement forms of the 3 input variables ci, x, and y, always produce minterms, never maxterms—that is, of the 8 gates required to process all combinations of 3 input variables, only one has the output value 1. That's because a NOR gate, despite its name, could better be viewed (using De Morgan's law) as the AND of the complements of its input signals. The reason this is not a problem is the duality of minterms and maxterms, i.e. each maxterm is the complement of the like-indexed minterm, and vice versa. In the minterm example above, we wrote
u
(
c
i
,
x
,
y
)
=
m
1
+
m
2
+
m
4
+
m
7
{\displaystyle u(ci,x,y)=m_{1}+m_{2}+m_{4}+m_{7}}
but to perform this with a 4-input NOR gate we need to restate it as a product of sums (PoS), where the sums are the opposite maxterms. That is,
u
(
c
i
,
x
,
y
)
=
A
N
D
(
M
0
,
M
3
,
M
5
,
M
6
)
=
N
O
R
(
m
0
,
m
3
,
m
5
,
m
6
)
.
{\displaystyle u(ci,x,y)=\mathrm {AND} (M_{0},M_{3},M_{5},M_{6})=\mathrm {NOR} (m_{0},m_{3},m_{5},m_{6}).}
In the maxterm example above, we wrote
c
o
(
c
i
,
x
,
y
)
=
M
0
M
1
M
2
M
4
{\displaystyle co(ci,x,y)=M_{0}M_{1}M_{2}M_{4}}
but to perform this with a 4-input NOR gate we need to notice the equality to the NOR of the same minterms. That is,